1. Field of Use
This invention relates generally to the scientific instruction processor floating point arithmetic operations and more specifically to the use of a programmable read only memory (PROM) to control the output of the mantissa digit shifters.
2. Description of the Prior Art
Scientific instruction processors perform floating point arithmetic operations. A floating point operand contains a mantissa, a mantissa sign and an exponent. The exponent indicates the position of the decimal point. Usually, the processor sets the exponent so as to form a fractional normalized mantissa, fractional in that the decimal point is to the left of the most significant digit position, and normalized in that the most significant digit position contains a digit other than zero. A digit may typically be in hexadecimal, decimal, octal, binary, coded decimal, binary bit, etc., form. Assuming a hexadecimal digit of 12A.6.times.16.sup.7 where 12A.6.sub.16 is the mantissa and 7.sub.16 is the exponent, the fractional normalized form is 0.12A6.times.16.sup.A. Certain floating point arithmetic operations require that the mantissa of one operand be shifted in accordance with the difference in exponents of the one operand with another operand. Also, there are requirements for left shift, right shift and shift around operations.
U.S. Pat. No. 4,130,879 entitled "Apparatus For Performing Floating Point Arithmetic Operations Using Submultiple Storage" describes a system using multidigit shifter logic circuits, shift control logic circuits, and multiplexer circuits to perform the shift operation. This system, however, has the problem of being slower and requires additional hardware for control of the shift operations.
It should be understood that the references cited herein are those of which the applicants are aware, and are presented to acquaint the reader with the level of skill in the art, and may not be the closest reference to the invention. No representation is made that any search has been conducted by the applicants.